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| author | jerryyin <zhuoryin@amd.com> | 2020-05-19 19:59:58 +0000 |
|---|---|---|
| committer | jerryyin <zhuoryin@amd.com> | 2020-05-21 14:14:35 +0000 |
| commit | 9c53ac08de7c5bfefab6e6c80127e6774070411c (patch) | |
| tree | 8afb57bb65db8d04310f90117734cfab82fbaf2a /llvm/lib/CodeGen/ModuloSchedule.cpp | |
| parent | c476abfd37c0578224c14fd90522fb825a0316fb (diff) | |
| download | llvm-9c53ac08de7c5bfefab6e6c80127e6774070411c.zip llvm-9c53ac08de7c5bfefab6e6c80127e6774070411c.tar.gz llvm-9c53ac08de7c5bfefab6e6c80127e6774070411c.tar.bz2 | |
[mlir][rocdl] Exposing buffer load/store intrinsic
Summary:
* Updated ROCDLOps tablegen
* Added parsing and printing function for new intrinsic
* Added unit tests
Reviewers: ftynse
Subscribers: mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, Kayjukh, jurahul, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D80233
Diffstat (limited to 'llvm/lib/CodeGen/ModuloSchedule.cpp')
0 files changed, 0 insertions, 0 deletions