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| author | Kazu Hirata <kazu@google.com> | 2022-06-25 11:56:50 -0700 |
|---|---|---|
| committer | Kazu Hirata <kazu@google.com> | 2022-06-25 11:56:50 -0700 |
| commit | 3b7c3a654c9175f41ac871a937cbcae73dfb3c5d (patch) | |
| tree | 21094939ea6c8b726c481d7b28eaf4ea27c64008 /llvm/lib/CodeGen/ModuloSchedule.cpp | |
| parent | aa8feeefd3ac6c78ee8f67bf033976fc7d68bc6d (diff) | |
| download | llvm-3b7c3a654c9175f41ac871a937cbcae73dfb3c5d.zip llvm-3b7c3a654c9175f41ac871a937cbcae73dfb3c5d.tar.gz llvm-3b7c3a654c9175f41ac871a937cbcae73dfb3c5d.tar.bz2 | |
Revert "Don't use Optional::hasValue (NFC)"
This reverts commit aa8feeefd3ac6c78ee8f67bf033976fc7d68bc6d.
Diffstat (limited to 'llvm/lib/CodeGen/ModuloSchedule.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/ModuloSchedule.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp index 37b851f..8e8cdb2 100644 --- a/llvm/lib/CodeGen/ModuloSchedule.cpp +++ b/llvm/lib/CodeGen/ModuloSchedule.cpp @@ -1447,8 +1447,8 @@ Register KernelRewriter::remapUse(Register Reg, MachineInstr &MI) { Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg, const TargetRegisterClass *RC) { // If the init register is not undef, try and find an existing phi. - if (InitReg) { - auto I = Phis.find({LoopReg, *InitReg}); + if (InitReg.hasValue()) { + auto I = Phis.find({LoopReg, InitReg.getValue()}); if (I != Phis.end()) return I->second; } else { @@ -1469,10 +1469,10 @@ Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg, return R; // Found a phi taking undef as input, so rewrite it to take InitReg. MachineInstr *MI = MRI.getVRegDef(R); - MI->getOperand(1).setReg(*InitReg); - Phis.insert({{LoopReg, *InitReg}, R}); + MI->getOperand(1).setReg(InitReg.getValue()); + Phis.insert({{LoopReg, InitReg.getValue()}, R}); const TargetRegisterClass *ConstrainRegClass = - MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); + MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue())); assert(ConstrainRegClass && "Expected a valid constrained register class!"); (void)ConstrainRegClass; UndefPhis.erase(I); @@ -1483,18 +1483,18 @@ Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg, if (!RC) RC = MRI.getRegClass(LoopReg); Register R = MRI.createVirtualRegister(RC); - if (InitReg) { + if (InitReg.hasValue()) { const TargetRegisterClass *ConstrainRegClass = MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); assert(ConstrainRegClass && "Expected a valid constrained register class!"); (void)ConstrainRegClass; } BuildMI(*BB, BB->getFirstNonPHI(), DebugLoc(), TII->get(TargetOpcode::PHI), R) - .addReg(InitReg ? *InitReg : undef(RC)) + .addReg(InitReg.hasValue() ? *InitReg : undef(RC)) .addMBB(PreheaderBB) .addReg(LoopReg) .addMBB(BB); - if (!InitReg) + if (!InitReg.hasValue()) UndefPhis[LoopReg] = R; else Phis[{LoopReg, *InitReg}] = R; |