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authorAditya Nandakumar <aditya_nandakumar@apple.com>2017-08-23 20:45:48 +0000
committerAditya Nandakumar <aditya_nandakumar@apple.com>2017-08-23 20:45:48 +0000
commitefd8a84cd58e392c9fe68300a17378dc49b61330 (patch)
tree1f5071d91223f86d00cc580551c16efa83d90783 /llvm/lib/CodeGen/MachineVerifier.cpp
parent950567aac4bcd7e6e5231d1874f2d3f30fff3412 (diff)
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[GISEl]: Translate phi into G_PHI
G_PHI has the same semantics as PHI but also has types. This lets us verify that the types in the G_PHI are consistent. This also allows specifying legalization actions for G_PHIs. https://reviews.llvm.org/D36990 llvm-svn: 311596
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineVerifier.cpp17
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index fcb5448..7429a7f 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -926,6 +926,23 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
report("Generic instruction accessing memory must have one mem operand",
MI);
break;
+ case TargetOpcode::G_PHI: {
+ LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+ if (!DstTy.isValid() ||
+ !std::all_of(MI->operands_begin() + 1, MI->operands_end(),
+ [this, &DstTy](const MachineOperand &MO) {
+ if (!MO.isReg())
+ return true;
+ LLT Ty = MRI->getType(MO.getReg());
+ if (!Ty.isValid() || (Ty != DstTy))
+ return false;
+ return true;
+ }))
+ report("Generic Instruction G_PHI has operands with incompatible/missing "
+ "types",
+ MI);
+ break;
+ }
case TargetOpcode::STATEPOINT:
if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
!MI->getOperand(StatepointOpers::NBytesPos).isImm() ||