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| author | Craig Topper <craig.topper@sifive.com> | 2021-08-18 09:40:57 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-08-18 10:22:00 -0700 |
| commit | d9ba1a9c5cac638a5cf3d23404509f7eeb434b7a (patch) | |
| tree | 7ffff1235b1f32ef114ca2c6f3c754b744ca85c6 /llvm/lib/CodeGen/MachineVerifier.cpp | |
| parent | 6cc11090a1ee0d4ce2d9eba38323b7fc2dc084b6 (diff) | |
| download | llvm-d9ba1a9c5cac638a5cf3d23404509f7eeb434b7a.zip llvm-d9ba1a9c5cac638a5cf3d23404509f7eeb434b7a.tar.gz llvm-d9ba1a9c5cac638a5cf3d23404509f7eeb434b7a.tar.bz2 | |
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
We normally select these when the root node is a sext_inreg, but
SimplifyDemandedBits can sometimes bypass the sext_inreg for some
users. This can create situation where sext_inreg+add/sub/mul/shl
is selected to a W instruction, and then the add/sub/mul/shl is
separately selected to a non-W instruction with the same inputs.
This patch tries to detect when it would still be ok to use a W
instruction without the sext_inreg by checking the direct users.
This can allow the W instruction to CSE with one created for a
sext_inreg+add/sub/mul/shl. To minimize complexity and cost of
checking, we make no attempt to determine if the CSE will happen
and just always use a W instruction when we can.
Differential Revision: https://reviews.llvm.org/D107658
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
0 files changed, 0 insertions, 0 deletions