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author | Matthias Braun <matze@braunis.de> | 2015-08-24 22:59:52 +0000 |
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committer | Matthias Braun <matze@braunis.de> | 2015-08-24 22:59:52 +0000 |
commit | b2b7ef1de8118095963e1c085467fc411bd7e56f (patch) | |
tree | 10da40c76c37d53e59e8197182bd65cfffde9301 /llvm/lib/CodeGen/MachineVerifier.cpp | |
parent | 008ff14acf9ce39d855dbeeb622e0598bbad0d93 (diff) | |
download | llvm-b2b7ef1de8118095963e1c085467fc411bd7e56f.zip llvm-b2b7ef1de8118095963e1c085467fc411bd7e56f.tar.gz llvm-b2b7ef1de8118095963e1c085467fc411bd7e56f.tar.bz2 |
MachineBasicBlock: Add liveins() method returning an iterator_range
llvm-svn: 245895
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index dc16772..078e576 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -507,11 +507,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { if (MRI->isSSA()) { // If this block has allocatable physical registers live-in, check that // it is an entry block or landing pad. - for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(), - LE = MBB->livein_end(); - LI != LE; ++LI) { - unsigned reg = *LI; - if (isAllocatable(reg) && !MBB->isLandingPad() && + for (unsigned LI : MBB->liveins()) { + if (isAllocatable(LI) && !MBB->isLandingPad() && MBB != MBB->getParent()->begin()) { report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB); } @@ -680,13 +677,12 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { } regsLive.clear(); - for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), - E = MBB->livein_end(); I != E; ++I) { - if (!TargetRegisterInfo::isPhysicalRegister(*I)) { + for (unsigned LI : MBB->liveins()) { + if (!TargetRegisterInfo::isPhysicalRegister(LI)) { report("MBB live-in list contains non-physical register", MBB); continue; } - for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true); + for (MCSubRegIterator SubRegs(LI, TRI, /*IncludeSelf=*/true); SubRegs.isValid(); ++SubRegs) regsLive.insert(*SubRegs); } |