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author | Thorsten Schütt <schuett@gmail.com> | 2024-07-18 16:22:37 +0200 |
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committer | GitHub <noreply@github.com> | 2024-07-18 16:22:37 +0200 |
commit | 1cc107234969c33a7036b9694da57f4223e3e4d7 (patch) | |
tree | a246cfe627286270efbee6c7ef8a7a950834d7f8 /llvm/lib/CodeGen/MachineVerifier.cpp | |
parent | cd495d2cdd84a22026a115c7e9923c27b196732e (diff) | |
download | llvm-1cc107234969c33a7036b9694da57f4223e3e4d7.zip llvm-1cc107234969c33a7036b9694da57f4223e3e4d7.tar.gz llvm-1cc107234969c33a7036b9694da57f4223e3e4d7.tar.bz2 |
[GlobalIsel] Add G_SCMP and G_UCMP instructions (#98894)
https://github.com/llvm/llvm-project/pull/83227
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 0a5b8bd..d22fbe3 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1544,6 +1544,36 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { break; } + case TargetOpcode::G_SCMP: + case TargetOpcode::G_UCMP: { + LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); + LLT SrcTy = MRI->getType(MI->getOperand(1).getReg()); + LLT SrcTy2 = MRI->getType(MI->getOperand(2).getReg()); + + if (SrcTy.isPointerOrPointerVector() || SrcTy2.isPointerOrPointerVector()) { + report("Generic scmp/ucmp does not support pointers as operands", MI); + break; + } + + if (DstTy.isPointerOrPointerVector()) { + report("Generic scmp/ucmp does not support pointers as a result", MI); + break; + } + + if ((DstTy.isVector() != SrcTy.isVector()) || + (DstTy.isVector() && + DstTy.getElementCount() != SrcTy.getElementCount())) { + report("Generic vector scmp/ucmp must preserve number of lanes", MI); + break; + } + + if (SrcTy != SrcTy2) { + report("Generic scmp/ucmp must have same input types", MI); + break; + } + + break; + } case TargetOpcode::G_EXTRACT: { const MachineOperand &SrcOp = MI->getOperand(1); if (!SrcOp.isReg()) { |