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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-01-02 23:04:44 +0700 |
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committer | GitHub <noreply@github.com> | 2025-01-02 23:04:44 +0700 |
commit | 11e482c4a32be6a315e5bf2ae7599cf10eb84836 (patch) | |
tree | bcfed6c55664f1659ac0138dd6a78c38481c84d2 /llvm/lib/CodeGen/MachineTraceMetrics.cpp | |
parent | 8ab88f11a12aaecb46f7b0eb5c13e7802258c1e1 (diff) | |
download | llvm-11e482c4a32be6a315e5bf2ae7599cf10eb84836.zip llvm-11e482c4a32be6a315e5bf2ae7599cf10eb84836.tar.gz llvm-11e482c4a32be6a315e5bf2ae7599cf10eb84836.tar.bz2 |
RegAllocGreedy: Add dummy priority advisor for writing MIR tests (#121207)
I regularly struggle reproducing failures in greedy due to changes
in priority when resuming the allocation from MIR vs. a complete
compilation starting at IR. That is, the fix in
e0919b189bf2df4f97f22ba40260ab5153988b14 did not really fix the
problem of the instruction distance mattering.
Add a way to bypass all of the priority heuristics for MIR tests,
by prioritizing only by virtual register number. Could also
give this a more specific name, like PrioritizeLowVirtRegNumber
Diffstat (limited to 'llvm/lib/CodeGen/MachineTraceMetrics.cpp')
0 files changed, 0 insertions, 0 deletions