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| author | Petr Penzin <penzin.dev@gmail.com> | 2024-11-19 14:20:55 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-19 14:20:55 -0800 |
| commit | 41c86ca714a68eea8c73cf57fba28718d466660b (patch) | |
| tree | aed0c6396ad595d358cd4d49fd4a166d93c085b7 /llvm/lib/CodeGen/MachineSink.cpp | |
| parent | 4d7df40c084d9c551761027f873a59ac83cb398d (diff) | |
| download | llvm-41c86ca714a68eea8c73cf57fba28718d466660b.zip llvm-41c86ca714a68eea8c73cf57fba28718d466660b.tar.gz llvm-41c86ca714a68eea8c73cf57fba28718d466660b.tar.bz2 | |
[RISCV] Add TT-Ascalon-d8 processor (#115100)
Ascalon is an out-of-order CPU core from Tenstorrent. Overview:
https://tenstorrent.com/ip/tt-ascalon
Adding 8-wide version, -mcpu=tt-ascalon-d8. Scheduling model will be
added in a separate PR.
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Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Diffstat (limited to 'llvm/lib/CodeGen/MachineSink.cpp')
0 files changed, 0 insertions, 0 deletions