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authorMatt Arsenault <Matthew.Arsenault@amd.com>2020-01-15 11:21:56 -0500
committerMatt Arsenault <Matthew.Arsenault@amd.com>2020-01-24 12:15:10 -0800
commitd8328c0b6240234c8036f16c081ab7e8dc98cce8 (patch)
tree3cab8b04e55a14a7ff6b84fb12cd4484ccce9741 /llvm/lib/CodeGen/MachineScheduler.cpp
parent84e035d8f1d635d202692e3c38c9c96aa1e08088 (diff)
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TableGen: Work around assert on Mips register definitions
This would hit the "Biggest class wasn't first" assert in getMatchingSubClassWithSubRegs in a future patch for EXTRACT_SUBREG handling. Mips defines 4 identical register classes (MSA128B, MSA128H, MSA128BW, MSA128D). These have the same set of registers, and only differ by the isel type. I believe this is an ill formed way of defining registers, that probably is just to work around the inconvenience of mixing different types in a single register class in DAG patterns. Since these all have the same size, they would all sort to the beginning, but you would not necessarily get the same super register at the front as the assert enforces. Breaking the ambiguity by also sorting by name doesn't work, since each of these register classes all want to be first. Force sorting of the original register class if the size is the same.
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
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