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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-04-01 16:38:51 +0300 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2024-05-21 20:54:39 +0200 |
| commit | cec1eab9bd6bfffcf39d0962c7ce220284fc7c1a (patch) | |
| tree | d3a27278ed6e81023e3d59ea9b73ebc6031e1167 /llvm/lib/CodeGen/MachineScheduler.cpp | |
| parent | e67f2cc3fc38cec2041cfb197ac4688ed3d16e7e (diff) | |
| download | llvm-cec1eab9bd6bfffcf39d0962c7ce220284fc7c1a.zip llvm-cec1eab9bd6bfffcf39d0962c7ce220284fc7c1a.tar.gz llvm-cec1eab9bd6bfffcf39d0962c7ce220284fc7c1a.tar.bz2 | |
MachineScheduler: Add parameter name comments
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineScheduler.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 78d581c..0858be6 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -1664,7 +1664,8 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) { if (ShouldTrackPressure) { // Update top scheduled pressure. RegisterOperands RegOpers; - RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false); + RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, + /*IgnoreDead=*/false); if (ShouldTrackLaneMasks) { // Adjust liveness and add missing dead+read-undef flags. SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); @@ -1698,7 +1699,8 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) { } if (ShouldTrackPressure) { RegisterOperands RegOpers; - RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false); + RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, + /*IgnoreDead=*/false); if (ShouldTrackLaneMasks) { // Adjust liveness and add missing dead+read-undef flags. SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); |