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| author | Craig Topper <craig.topper@sifive.com> | 2023-01-13 10:04:00 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-01-13 10:40:25 -0800 |
| commit | c8bd5343df642f98966cea7aabc6b26144ec87e1 (patch) | |
| tree | 14d7364acf078d7531701deaa3ac375767d13ff0 /llvm/lib/CodeGen/MachineScheduler.cpp | |
| parent | 8b7c1fbd9647a5a6ef246a6b5b2543ea0f5a2337 (diff) | |
| download | llvm-c8bd5343df642f98966cea7aabc6b26144ec87e1.zip llvm-c8bd5343df642f98966cea7aabc6b26144ec87e1.tar.gz llvm-c8bd5343df642f98966cea7aabc6b26144ec87e1.tar.bz2 | |
[DAGCombiner][RISCV] Pre-promote (zext (abs X)) to (abs (sext X)) when X has an illegal type.
Type legalization will insert a sign extend anyway. By doing it
early we can remove the zext. ComputeNumSignBits can't spot it
after type legalization because type legalization may expand
the abs to sra+xor+sub.
If the zext result type is larger than the type to be promoted to,
we'll promote to a legal type and then zext the rest of the way.
If the legal type is larger than the destination type we can promote
and then truncate.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D140509
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
0 files changed, 0 insertions, 0 deletions