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authorQingShan Zhang <qshanz@cn.ibm.com>2020-07-27 02:02:40 +0000
committerQingShan Zhang <qshanz@cn.ibm.com>2020-07-27 02:02:40 +0000
commita6e9f5264c855dfa5dda3c5940ffdaaf22d7e693 (patch)
tree0392f981ca7d2482cffe2a330025f8147698b748 /llvm/lib/CodeGen/MachineScheduler.cpp
parent194a4beedd1e09ff0de3710ea431d8d3facd59e1 (diff)
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[Scheduling] Improve group algorithm for store cluster
Store Addr and Store Addr+8 are clusterable pair. They have memory(ctrl) dependency on different loads. Current implementation will put these two stores into different group and miss to cluster them. Reviewed By: evandro Differential Revision: https://reviews.llvm.org/D84139
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineScheduler.cpp8
1 files changed, 7 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index d9d0a78..cec7a0c 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1653,7 +1653,13 @@ void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAG) {
unsigned ChainPredID = DAG->SUnits.size();
for (const SDep &Pred : SU.Preds) {
- if (Pred.isCtrl() && !Pred.isArtificial()) {
+ // We only want to cluster the mem ops that have the same ctrl(non-data)
+ // pred so that they didn't have ctrl dependency for each other. But for
+ // store instrs, we can still cluster them if the pred is load instr.
+ if ((Pred.isCtrl() &&
+ (IsLoad ||
+ (Pred.getSUnit() && Pred.getSUnit()->getInstr()->mayStore()))) &&
+ !Pred.isArtificial()) {
ChainPredID = Pred.getSUnit()->NodeNum;
break;
}