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| author | Weiming Zhao <weimingz@codeaurora.org> | 2016-11-03 21:49:08 +0000 |
|---|---|---|
| committer | Weiming Zhao <weimingz@codeaurora.org> | 2016-11-03 21:49:08 +0000 |
| commit | 962eaaea9c9ea5cff2254b1251474029e4fe6a3d (patch) | |
| tree | 5038d15eb2b2989a9964644888634950bc341d64 /llvm/lib/CodeGen/MachineScheduler.cpp | |
| parent | 5bc0323c11f88580de66acbd588ddef8d986329b (diff) | |
| download | llvm-962eaaea9c9ea5cff2254b1251474029e4fe6a3d.zip llvm-962eaaea9c9ea5cff2254b1251474029e4fe6a3d.tar.gz llvm-962eaaea9c9ea5cff2254b1251474029e4fe6a3d.tar.bz2 | |
[Cortex-M0] Atomic lowering
Summary: ARMv6m supports dmb etc fench instructions but not ldrex/strex etc. So for some atomic load/store, LLVM should inline instructions instead of lowering to __sync_ calls.
Reviewers: rengolin, efriedma, t.p.northover, jmolloy
Subscribers: efriedma, aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D26120
llvm-svn: 285969
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
0 files changed, 0 insertions, 0 deletions