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author | Saiyedul Islam <Saiyedul.Islam@amd.com> | 2020-05-29 14:16:07 +0000 |
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committer | Saiyedul Islam <Saiyedul.Islam@amd.com> | 2020-06-09 17:02:58 +0000 |
commit | 675cefbf60270f59057972e33365a09590fb3694 (patch) | |
tree | 3c34ea127a5979a94d9d511fab7cd1deae5e1e36 /llvm/lib/CodeGen/MachineScheduler.cpp | |
parent | 1c189d71dbb9ea0f8dd2f396c051c4c89e0ad2df (diff) | |
download | llvm-675cefbf60270f59057972e33365a09590fb3694.zip llvm-675cefbf60270f59057972e33365a09590fb3694.tar.gz llvm-675cefbf60270f59057972e33365a09590fb3694.tar.bz2 |
[AMDGPU] Introduce Clang builtins to be mapped to AMDGCN atomic inc/dec intrinsics
Summary:
__builtin_amdgcn_atomic_inc32(int *Ptr, int Val, unsigned MemoryOrdering, const char *SyncScope)
__builtin_amdgcn_atomic_inc64(int64_t *Ptr, int64_t Val, unsigned MemoryOrdering, const char *SyncScope)
__builtin_amdgcn_atomic_dec32(int *Ptr, int Val, unsigned MemoryOrdering, const char *SyncScope)
__builtin_amdgcn_atomic_dec64(int64_t *Ptr, int64_t Val, unsigned MemoryOrdering, const char *SyncScope)
First and second arguments gets transparently passed to the amdgcn atomic
inc/dec intrinsic. Fifth argument of the intrinsic is set as true if the
first argument of the builtin is a volatile pointer. The third argument of
this builtin is one of the memory-ordering specifiers ATOMIC_ACQUIRE,
ATOMIC_RELEASE, ATOMIC_ACQ_REL, or ATOMIC_SEQ_CST following C++11 memory
model semantics. This is mapped to corresponding LLVM atomic memory ordering
for the atomic inc/dec instruction using CLANG atomic C ABI. The fourth
argument is an AMDGPU-specific synchronization scope defined as string.
Reviewers: arsenm, sameerds, JonChesterfield, jdoerfert
Reviewed By: arsenm, sameerds
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, jfb, kerbowa, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D80804
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
0 files changed, 0 insertions, 0 deletions