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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-29 03:54:56 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-29 03:54:56 +0000 |
| commit | 5fddf091879e195d1f3ac83e8384ec1ff2882c23 (patch) | |
| tree | 9d2b770b44634e07da8c531c5a5517d36d7a3ca2 /llvm/lib/CodeGen/MachineScheduler.cpp | |
| parent | 1445b77e8c6da8e43ba12f86b010852b97aea4fb (diff) | |
| download | llvm-5fddf091879e195d1f3ac83e8384ec1ff2882c23.zip llvm-5fddf091879e195d1f3ac83e8384ec1ff2882c23.tar.gz llvm-5fddf091879e195d1f3ac83e8384ec1ff2882c23.tar.bz2 | |
AMDGPU/GlobalISel: Insert waterfall loop for vector indexing
The register index can only really be an SGPR. Lie that a VGPR index
is legal, and then rewrite the instruction in a waterfall loop to
handle the index.
llvm-svn: 357235
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
0 files changed, 0 insertions, 0 deletions