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| author | Martin Fink <martin@finkmartin.com> | 2023-01-26 15:25:58 +0100 |
|---|---|---|
| committer | Marco Elver <elver@google.com> | 2023-01-26 16:13:46 +0100 |
| commit | 1142e6c7c795de7f80774325a07ed49bc95a48c9 (patch) | |
| tree | aeb651b2a97c83343dfeedae27fb80c8a72be718 /llvm/lib/CodeGen/MachineScheduler.cpp | |
| parent | 0c64e1b68f36640ffe82fc90e6279c50617ad1cc (diff) | |
| download | llvm-1142e6c7c795de7f80774325a07ed49bc95a48c9.zip llvm-1142e6c7c795de7f80774325a07ed49bc95a48c9.tar.gz llvm-1142e6c7c795de7f80774325a07ed49bc95a48c9.tar.bz2 | |
[SelectionDAG] Add missing setValue calls in visitIntrinsicCall
Add missing setValue calls in SelectionDAGBuilder for mem-transfer
intrinsic calls. These setValue calls are required in order to propagate
pcsections metadata from IR to MIR.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D141048
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
0 files changed, 0 insertions, 0 deletions