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authorDaniel Jasper <djasper@google.com>2013-12-06 08:58:22 +0000
committerDaniel Jasper <djasper@google.com>2013-12-06 08:58:22 +0000
commit0d92abdfd230c9b1eadbda170d5daec947375cd6 (patch)
tree9e4e66a9a832943de471795ec2e29aeb8da45f6a /llvm/lib/CodeGen/MachineScheduler.cpp
parent223bda22f4496a047502f85a5feeab25cee1bb7f (diff)
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Fix bug introduced in r196517.
Not only does it trigger -Wparentheses, I think the assert actually relies on incorrect operator precedence. Also, the grammar as questionable, but I might not know enough about the problem at hand. llvm-svn: 196567
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineScheduler.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 6cfedcb..1503596 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -2175,8 +2175,9 @@ void GenericScheduler::SchedBoundary::bumpNode(SUnit *SU) {
// exceed the issue width.
const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
- assert(CurrMOps == 0 || (CurrMOps + IncMOps) <= SchedModel->getIssueWidth() &&
- "Cannot scheduling this instructions MicroOps in the current cycle.");
+ assert(
+ (CurrMOps == 0 || (CurrMOps + IncMOps) <= SchedModel->getIssueWidth()) &&
+ "Cannot schedule this instructions MicroOps in the current cycle.");
unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");