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| author | Ramkumar Ramachandra <ramkumar.ramachandra@codasip.com> | 2025-05-08 11:49:54 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-08 11:49:54 +0100 |
| commit | c4f723a7c3bb12ce4e247bcaed755c8d927f73a4 (patch) | |
| tree | 9dca6b3f8e25e4804efc9e39712e3c51e923b061 /llvm/lib/CodeGen/MachineRegisterInfo.cpp | |
| parent | 1484f82cbc62eab9c4c8f393b84c2f521bf882f6 (diff) | |
| download | llvm-c4f723a7c3bb12ce4e247bcaed755c8d927f73a4.zip llvm-c4f723a7c3bb12ce4e247bcaed755c8d927f73a4.tar.gz llvm-c4f723a7c3bb12ce4e247bcaed755c8d927f73a4.tar.bz2 | |
[LV] Strip unmaintainable MinBWs assert (#136858)
tryToWiden attempts to replace an Instruction with a Constant from SCEV,
but forgets to erase the Instruction from the MinBWs map, leading to an
assert in VPlanTransforms::truncateToMinimalBitwidths. Going forward,
the assertion in truncateToMinimalBitwidths is unmaintainable, as LV
could simplify the expression at any point: fix the bug by stripping the
unmaintable assertion.
Fixes #125278.
Diffstat (limited to 'llvm/lib/CodeGen/MachineRegisterInfo.cpp')
0 files changed, 0 insertions, 0 deletions