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| author | Christudasan Devadasan <christudasan.devadasan@amd.com> | 2024-02-05 18:32:23 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-05 18:32:23 +0530 |
| commit | 89ec940b4a8020e1399e019d845be1a2d2217f69 (patch) | |
| tree | 4b923edef3c0839c9c30a1d1d3fadf029f53edce /llvm/lib/CodeGen/MachineRegisterInfo.cpp | |
| parent | b31fffbc7f1e0491bf599e82b7195e320d26e140 (diff) | |
| download | llvm-89ec940b4a8020e1399e019d845be1a2d2217f69.zip llvm-89ec940b4a8020e1399e019d845be1a2d2217f69.tar.gz llvm-89ec940b4a8020e1399e019d845be1a2d2217f69.tar.bz2 | |
[AMDGPU] Insert spill codes for the SGPRs used for EXEC copy (#79428)
The SGPR registers used for preserving EXEC mask while lowering the
whole-wave register spills and copies should be preserved at the prolog
and epilog if they are in the CSR range. It isn't happening when there
is only wwm-copy lowered and there are no wwm-spills. This patch
addresses that problem.
Diffstat (limited to 'llvm/lib/CodeGen/MachineRegisterInfo.cpp')
0 files changed, 0 insertions, 0 deletions