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| author | Craig Topper <craig.topper@sifive.com> | 2021-02-19 18:56:08 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-02-19 19:12:20 -0800 |
| commit | 71b68fe532b3aa8dddf55d1945f26ee3ad3e9867 (patch) | |
| tree | e36726854881661d033da42a832761aed1776365 /llvm/lib/CodeGen/MachineRegisterInfo.cpp | |
| parent | 33b0c63775ce58014c55e285671e3315104a6076 (diff) | |
| download | llvm-71b68fe532b3aa8dddf55d1945f26ee3ad3e9867.zip llvm-71b68fe532b3aa8dddf55d1945f26ee3ad3e9867.tar.gz llvm-71b68fe532b3aa8dddf55d1945f26ee3ad3e9867.tar.bz2 | |
[RISCV] Teach our custom vector load/store intrinsic isel code to propagate memory operands if we have them.
We don't currently create memory operands for these intrinsics,
but there was a suggestion of using the indexed load/store
intrinsics to implement isel for scalable vector gather/scatter.
That may propagate the memory operand from the gather/scatter
ISD nodes.
Diffstat (limited to 'llvm/lib/CodeGen/MachineRegisterInfo.cpp')
0 files changed, 0 insertions, 0 deletions