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author | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2019-01-09 05:11:10 +0000 |
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committer | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2019-01-09 05:11:10 +0000 |
commit | dad8c6a1c9a32aea5c468f86c119c0dd244c164f (patch) | |
tree | 13466959a59faa0a8b64e3c53660425559612ac0 /llvm/lib/CodeGen/MachinePipeliner.cpp | |
parent | 17f10abe1a3f23a28ce13c1647e19196a76adb32 (diff) | |
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[NFC] fix trivial typos in comments
llvm-svn: 350690
Diffstat (limited to 'llvm/lib/CodeGen/MachinePipeliner.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachinePipeliner.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index de8c555..9d79e89 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -1557,7 +1557,7 @@ void SwingSchedulerDAG::Circuits::createAdjacencyStructure( } } } - // Add back-eges in the adjacency matrix for the output dependences. + // Add back-edges in the adjacency matrix for the output dependences. for (auto &OD : OutputDeps) if (!Added.test(OD.second)) { AdjK[OD.first].push_back(OD.second); @@ -2773,7 +2773,7 @@ void SwingSchedulerDAG::generateExistingPhis( else if (PrologStage >= AccessStage + StageDiff + np && VRMap[PrologStage - StageDiff - np].count(LoopVal) != 0) PhiOp1 = VRMap[PrologStage - StageDiff - np][LoopVal]; - // Check if the Phi has already been scheduled, but the loop intruction + // Check if the Phi has already been scheduled, but the loop instruction // is either another Phi, or doesn't occur in the loop. else if (PrologStage >= AccessStage + StageDiff + np) { // If the Phi references another Phi, we need to examine the other |