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authorThomas Preud'homme <thomasp@graphcore.ai>2022-10-21 15:42:56 +0100
committerThomas Preud'homme <thomasp@graphcore.ai>2022-11-07 09:53:41 +0000
commitc8be35293c82f216e975c56f62ddf9199a22f2e2 (patch)
treed3a6151ab24c3d27dc4d3d18125e795b39d46aef /llvm/lib/CodeGen/MachinePipeliner.cpp
parenteb421c0c0edf8420b00bc8d51bb1160c3eda9661 (diff)
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[SWP] Recognize mem carried dep with different base
The loop-carried dependency detection logic in isLoopCarriedDep relies on the load and store using the same definition for the base register. This misses the case of post-increment loads and stores whose base register are different PHI initialized from the same initial value. This commit extends the logic to accept the load and store having different PHI base address provided that they had the same initial value when entering the loop and are incremented by the same amount in each loop. Reviewed By: bcahoon Differential Revision: https://reviews.llvm.org/D136463
Diffstat (limited to 'llvm/lib/CodeGen/MachinePipeliner.cpp')
-rw-r--r--llvm/lib/CodeGen/MachinePipeliner.cpp26
1 files changed, 17 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 721bd52..3333cbd 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -2277,20 +2277,28 @@ bool SwingSchedulerDAG::isLoopCarriedDep(SUnit *Source, const SDep &Dep,
assert(!OffsetSIsScalable && !OffsetDIsScalable &&
"Expected offsets to be byte offsets");
- if (!BaseOpS->isIdenticalTo(*BaseOpD))
+ MachineInstr *DefS = MRI.getVRegDef(BaseOpS->getReg());
+ MachineInstr *DefD = MRI.getVRegDef(BaseOpD->getReg());
+ if (!DefS || !DefD || !DefS->isPHI() || !DefD->isPHI())
+ return true;
+
+ unsigned InitValS = 0;
+ unsigned LoopValS = 0;
+ unsigned InitValD = 0;
+ unsigned LoopValD = 0;
+ getPhiRegs(*DefS, BB, InitValS, LoopValS);
+ getPhiRegs(*DefD, BB, InitValD, LoopValD);
+ MachineInstr *InitDefS = MRI.getVRegDef(InitValS);
+ MachineInstr *InitDefD = MRI.getVRegDef(InitValD);
+
+ if (!InitDefS->isIdenticalTo(*InitDefD))
return true;
// Check that the base register is incremented by a constant value for each
// iteration.
- MachineInstr *Def = MRI.getVRegDef(BaseOpS->getReg());
- if (!Def || !Def->isPHI())
- return true;
- unsigned InitVal = 0;
- unsigned LoopVal = 0;
- getPhiRegs(*Def, BB, InitVal, LoopVal);
- MachineInstr *LoopDef = MRI.getVRegDef(LoopVal);
+ MachineInstr *LoopDefS = MRI.getVRegDef(LoopValS);
int D = 0;
- if (!LoopDef || !TII->getIncrementValue(*LoopDef, D))
+ if (!LoopDefS || !TII->getIncrementValue(*LoopDefS, D))
return true;
uint64_t AccessSizeS = (*SI->memoperands_begin())->getSize();