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| author | James Molloy <jmolloy@google.com> | 2019-04-19 09:00:55 +0000 |
|---|---|---|
| committer | James Molloy <jmolloy@google.com> | 2019-04-19 09:00:55 +0000 |
| commit | 9ad4cb3de47e3520adb4caf1dcadd33b72038493 (patch) | |
| tree | 14b894620cee51a58cb5fb61e51a1b5a739b6837 /llvm/lib/CodeGen/MachinePipeliner.cpp | |
| parent | 7137b54a03479ddef1d45314961bffff631453d3 (diff) | |
| download | llvm-9ad4cb3de47e3520adb4caf1dcadd33b72038493.zip llvm-9ad4cb3de47e3520adb4caf1dcadd33b72038493.tar.gz llvm-9ad4cb3de47e3520adb4caf1dcadd33b72038493.tar.bz2 | |
[PATCH] [MachineScheduler] Check pending instructions when an instruction is scheduled
Pending instructions that may have been blocked from being available by the HazardRecognizer may no longer may not be blocked any more when an instruction is scheduled; pending instructions should be re-checked in this case.
This is primarily aimed at VLIW targets with large parallelism and esoteric constraints.
No testcase as no in-tree targets have this behavior.
Differential revision: https://reviews.llvm.org/D60861
llvm-svn: 358743
Diffstat (limited to 'llvm/lib/CodeGen/MachinePipeliner.cpp')
0 files changed, 0 insertions, 0 deletions