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| author | Pierre van Houtryve <pierre.vanhoutryve@amd.com> | 2025-05-14 10:48:51 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-14 10:48:51 +0200 |
| commit | 4e63e0457cc1f768c628e71a0786fdb8a6ec271e (patch) | |
| tree | 94979aef53efaf1b869e9dffcce8d70d88ddebbe /llvm/lib/CodeGen/MachinePipeliner.cpp | |
| parent | d441d28083e2f9de5170f5a96a8e44a38d306c62 (diff) | |
| download | llvm-4e63e0457cc1f768c628e71a0786fdb8a6ec271e.zip llvm-4e63e0457cc1f768c628e71a0786fdb8a6ec271e.tar.gz llvm-4e63e0457cc1f768c628e71a0786fdb8a6ec271e.tar.bz2 | |
[AMDGPU] Canonicalize G_ZEXT of the shift amount in RegBankCombiner (#131792)
Canonicalize it to a G_AND instead so that ISel patterns can pick it
up and ignore it, as the shift instructions only read low bits.
G_ZEXT would be lowered to a v/s_and anyway in most cases.
I'm also looking at making a DAG version of this in a separate patch.
Diffstat (limited to 'llvm/lib/CodeGen/MachinePipeliner.cpp')
0 files changed, 0 insertions, 0 deletions