diff options
| author | Brandon Wu <songwu0813@gmail.com> | 2025-07-21 17:49:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-21 17:49:34 -0700 |
| commit | 24bf4aea0ca31c4733d8771751f7fb766c455aa9 (patch) | |
| tree | 8489adc596790b351e7bcaba31e646ec3e73f1a5 /llvm/lib/CodeGen/MachinePipeliner.cpp | |
| parent | 0c14f0e891ad88b9bb4666ef337466961b27314f (diff) | |
| download | llvm-24bf4aea0ca31c4733d8771751f7fb766c455aa9.zip llvm-24bf4aea0ca31c4733d8771751f7fb766c455aa9.tar.gz llvm-24bf4aea0ca31c4733d8771751f7fb766c455aa9.tar.bz2 | |
[RISCV][llvm] Handle vector callee saved register correctly (#149467)
In TargetFrameLowering::determineCalleeSaves, any vector register is
marked
as saved if any of its subregister is clobbered, this is not correct in
vector registers. We only want the vector register to be marked as saved
only if all of its subregisters are clobbered.
This patch handles vector callee saved registers in target hook.
Diffstat (limited to 'llvm/lib/CodeGen/MachinePipeliner.cpp')
0 files changed, 0 insertions, 0 deletions