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| author | Craig Topper <craig.topper@intel.com> | 2020-08-20 23:45:34 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-08-20 23:50:45 -0700 |
| commit | df9a9bb7beb7bc04ca4188fe0e527baac2900ff1 (patch) | |
| tree | c2d6c0a836cc2c2340d6df355759d18b3565fcce /llvm/lib/CodeGen/MachinePassManager.cpp | |
| parent | 927da43ade12fffc8077c248e0243711071b2094 (diff) | |
| download | llvm-df9a9bb7beb7bc04ca4188fe0e527baac2900ff1.zip llvm-df9a9bb7beb7bc04ca4188fe0e527baac2900ff1.tar.gz llvm-df9a9bb7beb7bc04ca4188fe0e527baac2900ff1.tar.bz2 | |
[X86] Correct the implementation of the testFeature macro in getIntelProcessorTypeAndSubtype to do a proper bit test.
Instead of ANDing with a one hot mask representing the bit to
be tested, we were ANDing with just the bit number. This tests
multiple bits none of them the correct one.
This caused skylake-avx512, cascadelake and cooperlake to all
be misdetected. Based on experiments with the Intel SDE, it seems
that all of these CPUs are being detected as being cooperlake.
This is bad since its the newest CPU of the 3.
Diffstat (limited to 'llvm/lib/CodeGen/MachinePassManager.cpp')
0 files changed, 0 insertions, 0 deletions