diff options
| author | Andrea Di Biagio <andrea.dibiagio@sony.com> | 2021-05-07 20:20:03 +0100 |
|---|---|---|
| committer | Andrea Di Biagio <andrea.dibiagio@sony.com> | 2021-05-07 21:30:25 +0100 |
| commit | 3822ac909ead8f41ebc81e382bb01908bf04f407 (patch) | |
| tree | c83232bdefe81738f5931c19da0f70f399155927 /llvm/lib/CodeGen/MachinePassManager.cpp | |
| parent | c4adc49a1c988e6ea8a340b6245525ef5599812c (diff) | |
| download | llvm-3822ac909ead8f41ebc81e382bb01908bf04f407.zip llvm-3822ac909ead8f41ebc81e382bb01908bf04f407.tar.gz llvm-3822ac909ead8f41ebc81e382bb01908bf04f407.tar.bz2 | |
[MCA][RegisterFile] Fix register class check for move elimination (PR50265)
The register file should always check if the destination register is from a
register class that allows move elimination.
Before this change, the check on the register class was only performed in a few
very specific cases. However, it should have always been performed.
This patch fixes the issue.
Note that none of the upstream scheduling models is currently affected by this
bug, so there is no test for it. The issue was found by Roman while working on
the znver3 model. I was able to reproduce the issue locally by tweaking the
btver2 model. I then verified that this patch fixes the issue.
Diffstat (limited to 'llvm/lib/CodeGen/MachinePassManager.cpp')
0 files changed, 0 insertions, 0 deletions