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| author | Chen Zheng <czhengsz@cn.ibm.com> | 2023-04-07 10:22:31 +0000 |
|---|---|---|
| committer | Chen Zheng <czhengsz@cn.ibm.com> | 2023-04-10 02:11:33 +0000 |
| commit | a3d5ec51bacfadb560cc78a7e866b118027a414e (patch) | |
| tree | 7c3e220477a02b5eac9ef3f5474d57d7d4a78f06 /llvm/lib/CodeGen/MachineOutliner.cpp | |
| parent | 08cf5360c2a5885f3ee879cd4b32fb9a74aae07f (diff) | |
| download | llvm-a3d5ec51bacfadb560cc78a7e866b118027a414e.zip llvm-a3d5ec51bacfadb560cc78a7e866b118027a414e.tar.gz llvm-a3d5ec51bacfadb560cc78a7e866b118027a414e.tar.bz2 | |
[AMDGPU][Global-ISel] reuse extension related patterns in td file
However the imported rules can not be used for now because Global ISel
selectImpl() seems has some bug/limitation to create a illegl COPY
from VGPR to SGPR. So currently workaround this by not auto selecting these
patterns.
Fixes #61468
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D147780
Diffstat (limited to 'llvm/lib/CodeGen/MachineOutliner.cpp')
0 files changed, 0 insertions, 0 deletions