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| author | Sam Parker <sam.parker@arm.com> | 2020-03-27 13:58:50 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2020-03-27 15:26:13 +0000 |
| commit | d7084fa34aea7ac9ddf18fbe25731d2c8d291db0 (patch) | |
| tree | 2d9541f5ddaa63c18a5a1b97635aa718172323f8 /llvm/lib/CodeGen/MachineOperand.cpp | |
| parent | ee27df5552de5a9e9ac536dd193d927368248d17 (diff) | |
| download | llvm-d7084fa34aea7ac9ddf18fbe25731d2c8d291db0.zip llvm-d7084fa34aea7ac9ddf18fbe25731d2c8d291db0.tar.gz llvm-d7084fa34aea7ac9ddf18fbe25731d2c8d291db0.tar.bz2 | |
[ARM][LowOverheadLoops] DoubleWidthResult instructions canGenerateZeros
Given that some instructions generate wider result elements than
their inputs, flag them as being able to generate non zeros in the
false lanes.
Differential Revision: https://reviews.llvm.org/D76766
Diffstat (limited to 'llvm/lib/CodeGen/MachineOperand.cpp')
0 files changed, 0 insertions, 0 deletions