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| author | Scott Linder <Scott.Linder@amd.com> | 2020-03-24 17:24:49 -0400 |
|---|---|---|
| committer | Scott Linder <Scott.Linder@amd.com> | 2020-03-26 14:43:25 -0400 |
| commit | bd12ecb88f0a3b9b3ca60814d20a7e9b0933f2ec (patch) | |
| tree | 67aa431bdfe010baee86206359b28e294fe7b9e2 /llvm/lib/CodeGen/MachineOperand.cpp | |
| parent | 9002db05a2f0d12681214fad3c96f8d497f2b852 (diff) | |
| download | llvm-bd12ecb88f0a3b9b3ca60814d20a7e9b0933f2ec.zip llvm-bd12ecb88f0a3b9b3ca60814d20a7e9b0933f2ec.tar.gz llvm-bd12ecb88f0a3b9b3ca60814d20a7e9b0933f2ec.tar.bz2 | |
[AMDGPU] Fix PC register mapping in wave32 mode
Summary:
The PC_32 DWARF register is for a 32-bit process address space which we
don't implement in AMDGCN; another way of putting this is that the size
of the PC register is not a function of the wavefront size. If we ever
implement a 32-bit process address space we will need to add two more
DwarfFlavours i.e. we will need to represent the product of (wave32,
wave64) x (64-bit address space, 32-bit address space).
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76732
Diffstat (limited to 'llvm/lib/CodeGen/MachineOperand.cpp')
0 files changed, 0 insertions, 0 deletions