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authorCraig Topper <craig.topper@gmail.com>2020-03-26 11:09:08 -0700
committerCraig Topper <craig.topper@gmail.com>2020-03-26 14:10:20 -0700
commit9f7d4150b9ec638a048c183c21a355195fdc4942 (patch)
tree175ac3f3d4f1ad9ce603a904b88bfa49b07cded9 /llvm/lib/CodeGen/MachineOperand.cpp
parent0731372ee25c8db93e0d976db4be4ffb7c7329c5 (diff)
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[X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.
These transforms rely on a vector reduction flag on the SDNode set by SelectionDAGBuilder. This flag exists because SelectionDAG can't see across basic blocks so SelectionDAGBuilder is looking across and saving the info. X86 is the only target that uses this flag currently. By removing the X86 code we can remove the flag and the SelectionDAGBuilder code. This pass adds a dedicated IR pass for X86 that looks across the blocks and transforms the IR into a form that the X86 SelectionDAG can finish. An advantage of this new approach is that we can enhance it to shrink the phi nodes and final reduction tree based on the zeroes that we need to concatenate to bring the partially reduced reduction back up to the original width. Differential Revision: https://reviews.llvm.org/D76649
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