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authorThorsten Schütt <schuett@gmail.com>2024-10-27 23:14:07 +0100
committerGitHub <noreply@github.com>2024-10-27 23:14:07 +0100
commit7b3da7b3b2b0e2f322dddf1f343571cc7fd09b09 (patch)
tree42545b400671a0804ed907debbd91d08e39066f1 /llvm/lib/CodeGen/MachineOperand.cpp
parent5621929f7f4878c318deecb592cd03f5ecbb83ba (diff)
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[GlobalISel][AArch64] Legalize G_ADD, G_SUB, G_AND, G_OR, and G_XOR for SVE (#110561)
Credits: https://github.com/llvm/llvm-project/pull/72976 LLVM ERROR: cannot select: %3:zpr(<vscale x 2 x s64>) = G_MUL %0:fpr, %1:fpr (in function: xmulnxv2i64) ;; mul define void @xmulnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, ptr %p) { entry: %c = mul <vscale x 2 x i64> %a, %b store <vscale x 2 x i64> %c, ptr %p, align 16 ret void } define void @mulnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, ptr %p) { entry: %c = mul <vscale x 4 x i32> %a, %b store <vscale x 4 x i32> %c, ptr %p, align 16 ret void } define void @mulnxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) { entry: %c = mul <vscale x 8 x i16> %a, %b store <vscale x 8 x i16> %c, ptr %p, align 16 ret void } define void @mulnxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, ptr %p) { entry: %c = mul <vscale x 16 x i8> %a, %b store <vscale x 16 x i8> %c, ptr %p, align 16 ret void }
Diffstat (limited to 'llvm/lib/CodeGen/MachineOperand.cpp')
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