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| author | Jay Foad <jay.foad@amd.com> | 2022-09-13 12:59:33 +0100 |
|---|---|---|
| committer | Jay Foad <jay.foad@amd.com> | 2022-09-13 20:26:08 +0100 |
| commit | 2e8863b6a11f12d31490bc054da4d47c6adc8143 (patch) | |
| tree | ef245b9e0db8e8facab88f0b6d83c9c9d10c674d /llvm/lib/CodeGen/MachineOperand.cpp | |
| parent | eda61fb656ab9e7b38330a94031ae1aac90eae3a (diff) | |
| download | llvm-2e8863b6a11f12d31490bc054da4d47c6adc8143.zip llvm-2e8863b6a11f12d31490bc054da4d47c6adc8143.tar.gz llvm-2e8863b6a11f12d31490bc054da4d47c6adc8143.tar.bz2 | |
[AMDGPU] Don't shrink VOP3 instructions pre-RA on GFX10+
In GFX10, there is no advantage to shrinking these instructions pre-RA,
so this just saves a bit of work.
In GFX11 there is an advantage to *not* shrinking them pre-RA, because
the register classes for 16-bit operands are less restrictive in the
VOP3 form than in the shrunk form. This patch is a prerequisite for
actually setting up those register classes correctly for 16-bit vs
non-16-bit operands.
Differential Revision: https://reviews.llvm.org/D133769
Diffstat (limited to 'llvm/lib/CodeGen/MachineOperand.cpp')
0 files changed, 0 insertions, 0 deletions