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| author | Gadi Haber <gadi.haber@intel.com> | 2017-12-08 09:48:44 +0000 |
|---|---|---|
| committer | Gadi Haber <gadi.haber@intel.com> | 2017-12-08 09:48:44 +0000 |
| commit | 2cf601f28f158cdce3c7640186e46a65bf308fc0 (patch) | |
| tree | 89247772dc39caf970e3be5da7d93b8c2d6bfff8 /llvm/lib/CodeGen/MachineOperand.cpp | |
| parent | 76b36d3a7f4237e2b923c532e9c350202a0c78b4 (diff) | |
| download | llvm-2cf601f28f158cdce3c7640186e46a65bf308fc0.zip llvm-2cf601f28f158cdce3c7640186e46a65bf308fc0.tar.gz llvm-2cf601f28f158cdce3c7640186e46a65bf308fc0.tar.bz2 | |
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget.
Updated the scheduling information for the Haswell subtarget with the following changes:
Regrouped the instructions after adding appropriate load + store latencies.
Added scheduling for missing instructions such as the GATHER instrs.
The changes were made after revisiting the latencies impact of all memory uOps.
Reviewers: RKSimon, zvi, craig.topper, apilipenko
Differential Revision: https://reviews.llvm.org/D40021
Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7
llvm-svn: 320137
Diffstat (limited to 'llvm/lib/CodeGen/MachineOperand.cpp')
0 files changed, 0 insertions, 0 deletions