diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-15 10:20:51 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-15 10:20:51 +0000 |
| commit | 0ad4c265d7202724a07c0473b5212d02b687c2d6 (patch) | |
| tree | 35a8e5aba5571d6614fb1f9410794235a77a5f13 /llvm/lib/CodeGen/MachineOperand.cpp | |
| parent | 74ecf59cc0e3a9306874508dd41f65606a693aa8 (diff) | |
| download | llvm-0ad4c265d7202724a07c0473b5212d02b687c2d6.zip llvm-0ad4c265d7202724a07c0473b5212d02b687c2d6.tar.gz llvm-0ad4c265d7202724a07c0473b5212d02b687c2d6.tar.bz2 | |
[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero
c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C.
This patch adds uimmlog2xlennonzero to reflect this constraint as well as
tests.
Differential Revision: https://reviews.llvm.org/D41216
Patch by Shiva Chen.
llvm-svn: 320799
Diffstat (limited to 'llvm/lib/CodeGen/MachineOperand.cpp')
0 files changed, 0 insertions, 0 deletions