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| author | Craig Topper <craig.topper@sifive.com> | 2025-02-06 10:29:45 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2025-02-06 10:29:45 -0800 |
| commit | 932d0ce32540467260bb04f6ee1ecd98a4efa245 (patch) | |
| tree | 9f3a63464a4b9583525040edd5c355573c98f11f /llvm/lib/CodeGen/MachineModuleInfoImpls.cpp | |
| parent | 2ef2587ae9d97d9325e9ecd11bcf4e3dff02e119 (diff) | |
| download | llvm-932d0ce32540467260bb04f6ee1ecd98a4efa245.zip llvm-932d0ce32540467260bb04f6ee1ecd98a4efa245.tar.gz llvm-932d0ce32540467260bb04f6ee1ecd98a4efa245.tar.bz2 | |
Recommit "[RISCV] Prefer (select (x < 0), y, z) -> x >> (XLEN - 1) & (y - z) + z even with Zicond. (#125772)"
With the test changes.
Original message:
The Zicond version of this requires an li instruction and an
additional register.
Without Zicond we match this in a DAGCombine on RISCVISD::SELECT_CC.
This PR has 2 commits. I'll pre-commit the test change if this looks
good.
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp')
0 files changed, 0 insertions, 0 deletions