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| author | Zakk Chen <zakk.chen@sifive.com> | 2020-12-27 20:00:33 -0800 |
|---|---|---|
| committer | Zakk Chen <zakk.chen@sifive.com> | 2020-12-28 18:57:17 -0800 |
| commit | f3f9ce3b7948b250bc532818ed76a64cea8b6fbe (patch) | |
| tree | ecd9c5140d7fca5e46d3980cf9059e4605999163 /llvm/lib/CodeGen/MachineModuleInfo.cpp | |
| parent | 8b67c98c4774313ab0ce5db1a975d2e69850368a (diff) | |
| download | llvm-f3f9ce3b7948b250bc532818ed76a64cea8b6fbe.zip llvm-f3f9ce3b7948b250bc532818ed76a64cea8b6fbe.tar.gz llvm-f3f9ce3b7948b250bc532818ed76a64cea8b6fbe.tar.bz2 | |
[RISCV] Define vmclr.m/vmset.m intrinsics.
Define vmclr.m/vmset.m intrinsics and lower to vmxor.mm/vmxnor.mm.
Ideally all rvv pseudo instructions could be implemented in C header,
but those two instructions don't take an input, codegen can not guarantee
that the source register becomes the same as the destination.
We expand pseduo-v-inst into corresponding v-inst in
RISCVExpandPseudoInsts pass.
Reviewed By: craig.topper, frasercrmck
Differential Revision: https://reviews.llvm.org/D93849
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfo.cpp')
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