diff options
| author | David Penry <david.penry@arm.com> | 2021-04-19 21:27:45 +0100 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2021-04-19 21:27:45 +0100 |
| commit | ca8eef7e3da8f750d7c7aa004fe426d1d34787ea (patch) | |
| tree | a98873502e504a4e3c24c6731ff9d9a7e3cce487 /llvm/lib/CodeGen/MachineModuleInfo.cpp | |
| parent | 78a871abf7018f4a288b773c9c89f99cd5c66b9c (diff) | |
| download | llvm-ca8eef7e3da8f750d7c7aa004fe426d1d34787ea.zip llvm-ca8eef7e3da8f750d7c7aa004fe426d1d34787ea.tar.gz llvm-ca8eef7e3da8f750d7c7aa004fe426d1d34787ea.tar.bz2 | |
[CodeGen] Use ProcResGroup information in SchedBoundary
When the ProcResGroup has BufferSize=0,
1. if there is a subunit in the list of write resources for the
scheduling class, do not attempt to schedule the ProcResGroup.
2. if there is not a subunit in the list of write resources for the
scheduling class, choose a subunit to use instead of the ProcResGroup.
3. having both the ProcResGroup and any of its subunits in the resources
implied by a InstRW is not supported.
Used to model parallel uses from a pool of resources.
Differential Revision: https://reviews.llvm.org/D98976
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfo.cpp')
0 files changed, 0 insertions, 0 deletions