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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-13 14:47:35 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-13 14:47:35 +0000 |
| commit | 6f590bf8bb3328f33dde73f50f1e408a13cf53a9 (patch) | |
| tree | 4e766be0d1a1a054476f355bc7fbf629a1bb557d /llvm/lib/CodeGen/MachineModuleInfo.cpp | |
| parent | 88e6f83f9eedf16ff0bff40f3714a1d64f2367c4 (diff) | |
| download | llvm-6f590bf8bb3328f33dde73f50f1e408a13cf53a9.zip llvm-6f590bf8bb3328f33dde73f50f1e408a13cf53a9.tar.gz llvm-6f590bf8bb3328f33dde73f50f1e408a13cf53a9.tar.bz2 | |
[PowerPC] MachineSSA pass to reduce the number of CR-logical operations
The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).
Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.
Differential Revision: https://reviews.llvm.org/D30431
llvm-svn: 320584
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfo.cpp')
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