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| author | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-05-29 09:03:27 +0000 |
|---|---|---|
| committer | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-05-29 09:03:27 +0000 |
| commit | 6c04ef3d48ab771b63d478aa9c338ad63c6f7836 (patch) | |
| tree | 42f1e37e1402e4cc4bbbae6ec6fb5987f8ab878f /llvm/lib/CodeGen/MachineModuleInfo.cpp | |
| parent | 75dfbdc2da1218cc19f18576a78109ef47ee5ff0 (diff) | |
| download | llvm-6c04ef3d48ab771b63d478aa9c338ad63c6f7836.zip llvm-6c04ef3d48ab771b63d478aa9c338ad63c6f7836.tar.gz llvm-6c04ef3d48ab771b63d478aa9c338ad63c6f7836.tar.bz2 | |
[AArch64][SVE2] Asm: support SVE Bitwise Logical - Unpredicated Group
Summary:
Patch adds support for the following instructions:
* EOR3, BSL, BCAX, BSL1N, BSL2N, NBSL, XAR
Aliases for types .B/.H/.S for EOR3 and BCAX have been added, the
preferred disassembly is .D.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62387
llvm-svn: 361936
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfo.cpp')
0 files changed, 0 insertions, 0 deletions