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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-11-20 17:04:36 +0300 |
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| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-11-20 17:57:50 +0300 |
| commit | 6778a62eb0d222dc625b8785516f027df12aaf16 (patch) | |
| tree | eaa6be7399b18755510ca79c746aa7ed60279693 /llvm/lib/CodeGen/MachineModuleInfo.cpp | |
| parent | a21940eac149dc03d9e028023bbd059f871af1c5 (diff) | |
| download | llvm-6778a62eb0d222dc625b8785516f027df12aaf16.zip llvm-6778a62eb0d222dc625b8785516f027df12aaf16.tar.gz llvm-6778a62eb0d222dc625b8785516f027df12aaf16.tar.bz2 | |
[AMDGPU][GFX10] Disabled v_movrel*[sdwa|dpp] opcodes in codegen
These opcodes use indirect register addressing so they need special handling by codegen (currently missing).
Reviewers: vpykhtin, arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D70400
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfo.cpp')
0 files changed, 0 insertions, 0 deletions