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| author | Hal Finkel <hfinkel@anl.gov> | 2013-05-16 19:58:38 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-05-16 19:58:38 +0000 |
| commit | 5f587c59a53f4daf44fc4f0679347bd00773885f (patch) | |
| tree | 31b4b238b7c045a86c7df97f0879f93bb5eb0916 /llvm/lib/CodeGen/MachineModuleInfo.cpp | |
| parent | fce4dd79748b270c5588f46cdb21a5e29103ce58 (diff) | |
| download | llvm-5f587c59a53f4daf44fc4f0679347bd00773885f.zip llvm-5f587c59a53f4daf44fc4f0679347bd00773885f.tar.gz llvm-5f587c59a53f4daf44fc4f0679347bd00773885f.tar.bz2 | |
Create an new preheader in PPCCTRLoops to avoid counter register clobbers
Some IR-level instructions (such as FP <-> i64 conversions) are not chained
w.r.t. the mtctr intrinsic and yet may become function calls that clobber the
counter register. At the selection-DAG level, these might be reordered with the
mtctr intrinsic causing miscompiles. To avoid this situation, if an existing
preheader has instructions that might use the counter register, create a new
preheader for the mtctr intrinsic. This extra block will be remerged with the
old preheader at the MI level, but will prevent unwanted reordering at the
selection-DAG level.
llvm-svn: 182045
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfo.cpp')
0 files changed, 0 insertions, 0 deletions