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| author | Lama Saba <lama.saba@intel.com> | 2017-05-18 08:11:50 +0000 |
|---|---|---|
| committer | Lama Saba <lama.saba@intel.com> | 2017-05-18 08:11:50 +0000 |
| commit | 2ea271b54a702adcb014eb9d072faa04d74c9a1b (patch) | |
| tree | b4a2d8d466d08b0c6dfedfea042f87d4bb80cf4c /llvm/lib/CodeGen/MachineModuleInfo.cpp | |
| parent | 994b6c9b8e7d0d22032aa66edd09701e8df1dfd1 (diff) | |
| download | llvm-2ea271b54a702adcb014eb9d072faa04d74c9a1b.zip llvm-2ea271b54a702adcb014eb9d072faa04d74c9a1b.tar.gz llvm-2ea271b54a702adcb014eb9d072faa04d74c9a1b.tar.bz2 | |
[X86] Replace slow LEA instructions in X86
According to Intel's Optimization Reference Manual for SNB+:
" For LEA instructions with three source operands and some specific situations, instruction latency has increased to 3 cycles, and must
dispatch via port 1:
- LEA that has all three source operands: base, index, and offset
- LEA that uses base and index registers where the base is EBP, RBP,or R13
- LEA that uses RIP relative addressing mode
- LEA that uses 16-bit addressing mode "
This patch currently handles the first 2 cases only.
Differential Revision: https://reviews.llvm.org/D32277
llvm-svn: 303333
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfo.cpp')
0 files changed, 0 insertions, 0 deletions