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| author | Dan Gohman <gohman@apple.com> | 2009-01-13 20:24:13 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-01-13 20:24:13 +0000 |
| commit | 1407484178b01896aac21aa88151f6192a8e4ed6 (patch) | |
| tree | c053c34f9dae0e128592926b5861ce0c6519e23d /llvm/lib/CodeGen/MachineModuleInfo.cpp | |
| parent | 59af77376c099516c7a54118dd69183658755371 (diff) | |
| download | llvm-1407484178b01896aac21aa88151f6192a8e4ed6.zip llvm-1407484178b01896aac21aa88151f6192a8e4ed6.tar.gz llvm-1407484178b01896aac21aa88151f6192a8e4ed6.tar.bz2 | |
The list-td and list-tdrr schedulers don't yet support physreg
scheduling dependencies. Add assertion checks to help catch
this.
It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.
llvm-svn: 62177
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfo.cpp')
0 files changed, 0 insertions, 0 deletions