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| author | Matthias Braun <matze@braunis.de> | 2015-08-31 18:25:15 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2015-08-31 18:25:15 +0000 |
| commit | 0acbd08f3c94fd719aef9d7a97679a1657ba220e (patch) | |
| tree | ac46ac1d2c1e5c7e48c77dbeeea8f975cb75a43a /llvm/lib/CodeGen/MachineModuleInfo.cpp | |
| parent | 818c78d0cc996c6289c30fb22d56637607b99e18 (diff) | |
| download | llvm-0acbd08f3c94fd719aef9d7a97679a1657ba220e.zip llvm-0acbd08f3c94fd719aef9d7a97679a1657ba220e.tar.gz llvm-0acbd08f3c94fd719aef9d7a97679a1657ba220e.tar.bz2 | |
AArch64: Fix loads to lower NEON vector lanes using GPR registers
The ISelLowering code turned insertion turned the element for the
lowest lane of a BUILD_VECTOR into an INSERT_SUBREG, this prohibited
the patterns for SCALAR_TO_VECTOR(Load) to match later. Restrict this
to cases without a load argument.
Reported in rdar://22223823
Differential Revision: http://reviews.llvm.org/D12467
llvm-svn: 246462
Diffstat (limited to 'llvm/lib/CodeGen/MachineModuleInfo.cpp')
0 files changed, 0 insertions, 0 deletions