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| author | Ramkumar Ramachandra <ramkumar.ramachandra@codasip.com> | 2025-02-06 18:14:54 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-06 18:14:54 +0000 |
| commit | f5d24e6cbe07902bad620df291f6172b50a7271e (patch) | |
| tree | 11ea898bbc272b5d0f8cdf4aaa1b2d19b7045785 /llvm/lib/CodeGen/MachineLoopUtils.cpp | |
| parent | dcb124e820b2bf9dda60f66151591155a385580e (diff) | |
| download | llvm-f5d24e6cbe07902bad620df291f6172b50a7271e.zip llvm-f5d24e6cbe07902bad620df291f6172b50a7271e.tar.gz llvm-f5d24e6cbe07902bad620df291f6172b50a7271e.tar.bz2 | |
SCEV: teach isImpliedViaOperations about samesign (#124270)
Use CmpPredicate::getMatching in isImpliedCondBalancedTypes to pass
samesign information to isImpliedViaOperations, and teach it to call
CmpPredicate::getPreferredSignedPredicate, effectively making it
optimize with samesign information.
Diffstat (limited to 'llvm/lib/CodeGen/MachineLoopUtils.cpp')
0 files changed, 0 insertions, 0 deletions