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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2021-09-24 11:12:59 -0700 |
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| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2021-10-20 11:46:50 -0700 |
| commit | 618583565687f5a494066fc902a977f6057fc93e (patch) | |
| tree | 7a39d72cc29dbce03ef25da436803811b2d7e58c /llvm/lib/CodeGen/MachineLoopInfo.cpp | |
| parent | 5d57578a4e48e4b4cdd41533670a012ad265c8a1 (diff) | |
| download | llvm-618583565687f5a494066fc902a977f6057fc93e.zip llvm-618583565687f5a494066fc902a977f6057fc93e.tar.gz llvm-618583565687f5a494066fc902a977f6057fc93e.tar.bz2 | |
[AMDGPU] Allow rematerialization of SOP with virtual registers
D106408 was doing this for all targets although it was
reverted due to couple performance regressions on some targets.
The difference for AMDGPU is the ability to rematerialize SOP
instructions with virtual register uses like we already do for VOP.
Differential Revision: https://reviews.llvm.org/D110743
Diffstat (limited to 'llvm/lib/CodeGen/MachineLoopInfo.cpp')
0 files changed, 0 insertions, 0 deletions