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| author | David Green <david.green@arm.com> | 2021-05-24 11:26:45 +0100 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2021-05-24 11:26:45 +0100 |
| commit | 53c42f7700e824d6ec394614653abd8b33d5da34 (patch) | |
| tree | 7b923b9076f8dd0ab14f5a42dcb3a947045e8263 /llvm/lib/CodeGen/MachineLoopInfo.cpp | |
| parent | 6cc78b9245bcc0e7a52723e2c298d290284e779b (diff) | |
| download | llvm-53c42f7700e824d6ec394614653abd8b33d5da34.zip llvm-53c42f7700e824d6ec394614653abd8b33d5da34.tar.gz llvm-53c42f7700e824d6ec394614653abd8b33d5da34.tar.bz2 | |
[ARM] Ensure WLS preheader blocks have branches during memcpy lowering
This makes sure that the blocks created for lowering memcpy to loops end
up with branches, even if they fall through to the successor. Otherwise
IfCvt is getting confused with unanalyzable branches and creating
invalid block layouts.
The extra branches should be removed as the tail predicated loop is
finalized in almost all cases.
Diffstat (limited to 'llvm/lib/CodeGen/MachineLoopInfo.cpp')
0 files changed, 0 insertions, 0 deletions