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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2023-03-20 18:49:17 -0400 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2023-06-20 12:26:27 -0400 |
commit | 7dcb9c0f09f89e2d6f527a480f214cf872c85b20 (patch) | |
tree | 87b0ff95463af3813022beb5cc0be72198dd7297 /llvm/lib/CodeGen/MachineInstrBundle.cpp | |
parent | 29ce3678c0188a4c9ee6576934c3e4abd72ff12d (diff) | |
download | llvm-7dcb9c0f09f89e2d6f527a480f214cf872c85b20.zip llvm-7dcb9c0f09f89e2d6f527a480f214cf872c85b20.tar.gz llvm-7dcb9c0f09f89e2d6f527a480f214cf872c85b20.tar.bz2 |
InlineSpiller: Consider copy bundles when looking for snippet copies
This was looking for full copies produced by SplitKit, but SplitKit
introduces copy bundles if not all lanes are live. The scan for uses
needs to look at bundles, not individual instructions.
This is a prerequisite to avoiding some redundant spills due to
subregisters which will help avoid an allocation failure in a future
patch.
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstrBundle.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineInstrBundle.cpp | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineInstrBundle.cpp b/llvm/lib/CodeGen/MachineInstrBundle.cpp index a952a98..b9db34f 100644 --- a/llvm/lib/CodeGen/MachineInstrBundle.cpp +++ b/llvm/lib/CodeGen/MachineInstrBundle.cpp @@ -307,6 +307,34 @@ VirtRegInfo llvm::AnalyzeVirtRegInBundle( return RI; } +std::pair<LaneBitmask, LaneBitmask> +llvm::AnalyzeVirtRegLanesInBundle(const MachineInstr &MI, Register Reg, + const MachineRegisterInfo &MRI, + const TargetRegisterInfo &TRI) { + + LaneBitmask UseMask, DefMask; + + for (ConstMIBundleOperands O(MI); O.isValid(); ++O) { + const MachineOperand &MO = *O; + if (!MO.isReg() || MO.getReg() != Reg) + continue; + + unsigned SubReg = MO.getSubReg(); + if (SubReg == 0 && MO.isUse() && !MO.isUndef()) + UseMask |= MRI.getMaxLaneMaskForVReg(Reg); + + LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); + if (MO.isDef()) { + if (!MO.isUndef()) + UseMask |= ~SubRegMask; + DefMask |= SubRegMask; + } else if (!MO.isUndef()) + UseMask |= SubRegMask; + } + + return {UseMask, DefMask}; +} + PhysRegInfo llvm::AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg, const TargetRegisterInfo *TRI) { bool AllDefsDead = true; |