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author | Florian Hahn <flo@fhahn.com> | 2019-12-02 20:00:56 +0000 |
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committer | Florian Hahn <flo@fhahn.com> | 2019-12-02 20:47:08 +0000 |
commit | 5154b0253d262be12d8f21edefd8c6d231dcf7a1 (patch) | |
tree | 973512357e9388181a1b65764baa5495b79ec323 /llvm/lib/CodeGen/MachineInstrBundle.cpp | |
parent | 7d019d1a3be252a885e8db1ee7af11c90b450d38 (diff) | |
download | llvm-5154b0253d262be12d8f21edefd8c6d231dcf7a1.zip llvm-5154b0253d262be12d8f21edefd8c6d231dcf7a1.tar.gz llvm-5154b0253d262be12d8f21edefd8c6d231dcf7a1.tar.bz2 |
[MIBundles] Move analyzePhysReg out of MIBundleOperands iterator (NFC).
analyzePhysReg does not really fit into the iterator and moving it
makes it easier to change the base iterator.
Reviewers: evandro, t.p.northover, paquette, MatzeB, arsenm, qcolombet
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D70559
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstrBundle.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineInstrBundle.cpp | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/MachineInstrBundle.cpp b/llvm/lib/CodeGen/MachineInstrBundle.cpp index ac9393b..94865b0 100644 --- a/llvm/lib/CodeGen/MachineInstrBundle.cpp +++ b/llvm/lib/CodeGen/MachineInstrBundle.cpp @@ -308,20 +308,15 @@ VirtRegInfo llvm::AnalyzeVirtRegInBundle( return RI; } -//===----------------------------------------------------------------------===// -// MachineOperand iterator -//===----------------------------------------------------------------------===// - -MachineOperandIteratorBase::PhysRegInfo -MachineOperandIteratorBase::analyzePhysReg(unsigned Reg, - const TargetRegisterInfo *TRI) { +PhysRegInfo llvm::AnalyzePhysRegInBundle(const MachineInstr &MI, unsigned Reg, + const TargetRegisterInfo *TRI) { bool AllDefsDead = true; PhysRegInfo PRI = {false, false, false, false, false, false, false, false}; assert(Register::isPhysicalRegister(Reg) && "analyzePhysReg not given a physical register!"); - for (; isValid(); ++*this) { - MachineOperand &MO = deref(); + for (ConstMIBundleOperands O(MI); O.isValid(); ++O) { + const MachineOperand &MO = *O; if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) { PRI.Clobbered = true; |